-------------------------------------------------------------------------------
-- cache_controller_pack.vhd
-------------------------------------------------------------------------------
--
-- This file is part of SKUMLI.
-- Copyright (C) 2011 Davide Giuseppe Monaco (black.ralkass@gmail.com)
--
-- SKUMLI is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- SKUMLI is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with SKUMLI.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
package cache_controller_pack is 

  component cache_controller is

    generic ( N : integer := 32 );

    port (
      -- control unit signals
      rw              : in  std_logic;
      cs              : in  std_logic;
      rdy             : out std_logic;

      -- address
      addr            : in  std_logic_vector(N - 1 downto 0);

      -- data input
      din             : in  std_logic_vector(N - 1 downto 0);

      -- data output
      dout            : out std_logic_vector(N - 1 downto 0);

    -- MEM HIERARCHY SIGNALS

      -- Input Signals
      -- main memory
      m_rdy           : in  std_logic;

      -- victim cache
      v_rdy           : in  std_logic;
      v_hit           : in  std_logic;
      v_tab           : in  std_logic_vector(29 downto 0);
      v_tab_buf       : in  std_logic_vector(29 downto 0);

      -- cache
      c_rdy           : in  std_logic;
      c_hit           : in  std_logic;
      c_tab           : in  std_logic_vector(24 downto 0);
      c_dout          : in  std_logic_vector(N - 1 downto 0);

      -- Output Signals
      -- main memory
      m_rw            : out std_logic;
      m_cs            : out std_logic;
      m_addr          : out std_logic_vector(N - 1 downto 0);

      -- victim cache
      v_rw            : out std_logic;
      v_cs            : out std_logic;
      v_addr          : out std_logic_vector(N - 1 downto 0);
      v_set_v         : out std_logic;
      v_set_d         : out std_logic;

      -- cache
      c_rw            : out std_logic;
      c_cs            : out std_logic;
      c_addr          : out std_logic_vector(N - 1 downto 0);
      c_set_v         : out std_logic;
      c_din_src       : out std_logic;

      -- Internal Signals
      -- cache input selector
      mux_ch_din_sel  : out std_logic_vector(1 downto 0);
      mux_ch_dout_sel : out std_logic_vector(1 downto 0);

      -- in buffers, to victim cache
      in_buf0_we      : out std_logic;
      in_buf1_we      : out std_logic;
      in_buf2_we      : out std_logic;
      in_buf3_we      : out std_logic;
      mux_in_buf_sel  : out std_logic_vector(1 downto 0);

      -- out buffers, from victim cache
      v_tab_buf_we    : out std_logic;
      out_buf0_we     : out std_logic;
      out_buf1_we     : out std_logic;
      out_buf2_we     : out std_logic;
      out_buf3_we     : out std_logic;
      mux_out_buf_sel : out std_logic_vector(1 downto 0)
    );
    
  end component;

end cache_controller_pack;
